Although the present invention deals with all kind of testers for electronic devices, the associated problems which form the basis of the present invention will first be discussed for the case of integrated circuit testers.
Integrated circuit testers are, in general, provided to test the functionality of IC's prior to their insertion or installation in an assembly, such as soldering on a printed circuit board. If any malfunction of an IC were only detectable on the board level (e.g., by a board tester), there would be a need to throw away the complete board, or at least the need for costly measures would arise, such as removal of the defective IC. Thus, integrated circuit testers ensure that defective IC's are detected in an early stage of assembly. This aspect is becoming more and more important with increasing integration, i.e., increasing package density of semiconductor chips.
In the past, different concepts have been used to test integrated circuits containing logic circuitry, and integrated circuits containing memories. The first group of devices has often been referred to as "LSI testers", whereas the latter group has been referred to as "memory testers".
Another approach to classify integrated circuit testers is by their internal structure. Two general concepts are known in the art, namely the "shared resource" approach and the "distributed resource" or "per pin resource" approach.
It is important to note that integrated circuit testers comprise logic circuitry which is dedicated to a specific terminal (pin) of the device to be tested (the so-called "Device under Test" or "DUT"). In other words, the same kind of logic circuitry exists multiple times in an IC tester, once for every pin of the DUT. If the IC tester is set up to test DUT's with a given maximum n of pins, this means that the pin circuitry has to be provided n times: n can approximate several hundred or even exceed some thousand, in view of state-of-the-art semiconductor chips and the related packaging technology.
The pin circuitry (pin channel or terminal channel) commonly comprises driver circuits for the assigned pin, and mostly also formatter and comparator circuits. The latter are circuits which combine data and timing information (formatter), or test a signal received from the assigned terminal for its timing and correct logic state (comparator). Reference is made to EP-B-329 798 and European Patent Application . . . (application number: 91119190.6) which disclose formatters of the kind discussed herein, and to DE-C-33 46 942, EP-B-325 670 and European Patent Application . . . (application number: 91119165.8), as far as comparators are concerned.
However, there is also circuitry which has not necessarily to be assigned to every pin of the DUT, like various control circuits. "Shared resource" in this context means that the control circuitry, or part thereof, is shared between multiple pins. For example, the control circuitry may be provided only once, and communicate with the pin channels (terminal channels) via a common bus. This eliminates the need to replicate the control circuit for every pin of the DUT. However, it implies several design constraints, particularly speed constraints.
In contrast, the "per pin resource" approach provides control circuitry, or at least the speed-critical part thereof, for every pin channel. This approach may overcome the above speed restrictions; however, it may be very expensive as the control circuitry has to be provided n times. Sometimes even the speed of a "per pin" resource does not fit the requirements of a particular application.
In the case of classic memory testers, a central algorithmic pattern generator (APG) has been provided (as a shared resource for all pin channels). The APG was an extremely complex and costly device, consisting of several PC boards or at least customized IC's (ASICs). Typically, it provided a first generator for the x addresses of the DUT, a second generator for the y addresses, a (third) data generator and a controller. Their operation can be illustrated by the creation of a zero pattern in the DUT. In this case, the data generator would generate a permanent "0". The X address generator would run from "0" to a predefined end address, whereas the y address generator would keep its value. As soon as the x address generator would reach its end address, it would be reset to "0"; the y address generator would be increased by one, and the x address generator would again run from "0" to its end address. The whole process would go on until all cells of the memory under test contained a "0".
The controller of such a prior art APG includes a programmable memory which contains the sequences to be generated, or a program which generates such sequences.
A tester designed essentially according to the "shared resource" approach is, for example, disclosed in U.S. Pat. No 4,450,560.
It is understood that, due to the interconnection of the control signals and the propagation delay times caused thereby, an APG of conventional design can operate only at limited speed. This applies even if very fast and expensive APG's are used, as has been common practice in the prior art.
Thus, prior art memory testers using the "shared resource" concept do not fit the need to test memories at acceptable speed. This applies particularly as the capacity of memories is increasing, and as there is a need to increase the rate of testing.
Another problem arises as more and more integrated circuits contain logic circuitry, as well as memories, on the same chip. This applies particularly to customized IC's such as ASICs. It would hardly be possible to test such devices with prior art IC testers designated specifically to memory or logic test in a given time frame. Even a combined tester incorporating memory and logic test circuitry would not fit those needs: Such a tester would have to provide different circuitry for pins designated as logic pins, as compared to pins designated as memory pins. However, as the designation of an ASIC's pin is not predefined, and as different ASICs have different pin designations, there would be an ongoing need to exchange or rearrange the pin channels, and their connection to a central resource. Even worse, there are integrated circuit devices which change their pin definition during operation. Such a device could not be tested with a combined memory/IC tester at all.
The above-mentioned U.S. Pat. No. 4,450,560 discloses an approach for a combined logic/memory tester wherein a switch is provided for switching between the two modes. However, this switch is complex and expensive and reduces operating speed. Speed is further reduced as this prior art tester uses the "shared resource" concept. Furthermore, the prior art tester is not able to deal with changing pin definitions within acceptable time limits.
In this context, it is important to note that prior art logic testers (LSI testers) are based on a different concept, as compared to memory testers. A so-called sequencer (basically a counter with some additional control circuitry, such that it can perform jumps, subroutines etc.) generates addresses which are fed to a memory. The memory--which is referred to herein as "Vector Memory"--decodes the addresses and feeds the data stored at the corresponding addresses to a pin-specific circuitry, usually called "formatter/comparator" circuit. The formatter processes the data received from the Vector Memory and links them with timing information, usually produced by edge generators. Likewise, the comparator checks data produced by the DUT for their accuracy in timing, as well as their correct logic state. Both the formatter and the comparator are connected with a single pin of the device under test.
A more advanced approach of decoding the sequencer addresses is described in European Patent Application . . . (application no. 91119189.8), which is fully incorporated herein by reference. The concept disclosed in this document uses an additional memory, called "Waveform Memory", to decode the output of the Vector Memory into a variety of actions, such that a multiplicity of operations on the DUT is possible, and wherein the definition of such actions may easily be changed by simply replacing the contents of the Waveform Memory. By the way, the Vector Memory/Waveform Memory approach may also be used in the present invention (see discussion below).
Prior art logic testers used the shared resource approach as well; i.e., the sequencer has been provided as a central resource, whereas the Vector Memories, the formatters and the comparators were provided per pin. This concept was subject to the same limitations in timing, as was the case for memory testers using the shared resource concept. Thus, logic testers based on the "per pin" approach have also been developed. That is, a specific sequencer has been provided for every pin channel. The various "pin" sequencers were all identical, i.e., executed the same program. The adaptation to the specific pin was performed by different data stored in the respective Vector Memories. This concept was commercially successful because a sequencer is a relatively simple and inexpensive unit, such that even a multiplicity of sequencers did not considerably increase the overall price of the logic tester.
However, all of these prior art solutions were not suited for a combined IC tester which should, by definition, be able to test mixed logic/memory circuitry, such as the above described ASICs, reliably and quickly, even when pin definitions change over time or from IC to IC. Consequently, there is a need for such a tester.
Likewise, there is an ongoing need for a memory tester which operates faster than prior art memory testers, at a reasonable price. The present invention focuses on solutions for both underlying problems.
It would also be desirable to have a logic tester which operates faster, and requires less hardware, than prior art logic testers.
It will be appreciated that similar problems exist in the field of board testers and other electronic device testing equipment. Board testers, for example, are provided either to test blank boards--i.e., unloaded boards wherein only the electrical connections are of interest--, or loaded boards. Whereas the first case is trivial, the second requires extensive testing circuitry, as the components on the boards may fulfil a variety of functions. It will be appreciated that a board tester in this sense may be even more complex than an integrated circuit tester, as a board may be loaded with components of different technology, e.g., digital logic circuitry, memories, analog circuitry and the like. Thus, there is also a need for a board tester which is sufficiently fast and can test all the functions on the board, at a reasonable price.
It will be understood that the present invention focuses also on related electronic device testers, such as board testers, ASIC testers, and so on.